TPPAT=00, SYEREN=0, RPPAT=00, SYNSEL=0, TMPOL=0, TPLEN=0x0, SBEREN=0, SBSEL=0, ERTEN=0, RMPOL=0, PFEREN=0, RPLEN=Others
Manchester Control Register
| RMPOL | Polarity of Received Manchester Code 0 (0): Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code 1 (1): Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code |
| TMPOL | Polarity of Transmit Manchester Code 0 (0): Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code 1 (1): Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code |
| ERTEN | Manchester Edge Retiming Enable 0 (0): Disables the receive retiming function 1 (1): Enables the receive retiming function |
| SYNVAL | SYNC value Setting |
| SYNSEL | SYNC Select 0 (0): The start bit pattern is set with the SYNVAL bit 1 (1): The start bit pattern is set with the TSYNC bit. |
| SBSEL | Start Bit Select 0 (0): The start bit area consists of one bit. 1 (1): The start bit area consists of three bits (COMMAND SYNC or DATA SYNC) |
| TPLEN | Transmit preface length 0 (Others): Transmit preface length (bit length) 0 (0x0): Disables the transmit preface generation |
| TPPAT | Transmit preface pattern 0 (00): ALL ZERO 1 (01): ZERO ONE 2 (10): ONE ZERO 3 (11): ALL ONE |
| RPLEN | Receive Preface Length 0 (0x0): Disables the receive preface generation 0 (Others): Receive preface length (bit length) |
| RPPAT | Receive Preface Pattern 0 (00): ALL ZERO 1 (01): ZERO ONE 2 (10): ONE ZERO 3 (11): ALL ONE |
| PFEREN | Preface Error Enable 0 (0): Does not handle a preface error as an interrupt source 1 (1): Handles a preface error as an interrupt source |
| SYEREN | Receive SYNC Error Enable 0 (0): Does not handle a receive SYNC error as an interrupt source 1 (1): Handles a receive SYNC error as an interrupt source |
| SBEREN | Start Bit Error Enable 0 (0): Does not handle a start bit error as an interrupt source 1 (1): Handles a start bit error as an interrupt source |